1. Field of the Invention
The present invention relates to a testing device for testing a digital information processor, and, more particularly, to a testing device which performs testing by causing a simulated failure to occur at a printed circuit board in an operation state.
2. Description of the Related Art
Hitherto, parallel scanning and serial scanning have been available as methods of testing a digital information processor. In each of these methods, as shown in each of the respective examples illustrated in FIGS. 6 and 7, a circuit designed exclusively for testing is added to a printed circuit board 600, 700, the state of flip-flop (FF) 601, 602, 701, 702 in a digital circuit is arbitrarily set while monitoring an output, and a failure is detected when an output corresponding to the set state cannot be obtained. AND circuit 603 is included in parallel scanning.
However, in these methods, as the size of the digital circuit is increased, the proportion occupied by the added circuit designed exclusively for testing in comparison with the size of the actual digital circuit is increased to a proportion that cannot be ignored. In addition, in the serial scanning method, in order to set each FF 601, 602, 701, 702 state, the device must be stopped once.
A testing method which uses an X-Y robot and which monitors a signal level at any point on a printed circuit board is disclosed (refer to Japanese Unexamined Patent Application Publication No. 11-94907 (hereafter “Patent Document”)).
In the method described in Patent Document, as shown in FIG. 8, an X-Y robot which holds a printed circuit board of a device to be tested is used, a probe tip of a probe is moved in accordance with a movement command from a personal computer and is brought into contact with a via hole and/or a land to be tested, the output from the probe is monitored, and the output is compared with a predetermined signal level in order to determine whether the device to be tested is in a normal state or an abnormal state.
FIG. 9 shows in detail the X-Y robot in the testing structure shown in FIG. 8. The method illustrated in FIG. 9 is a method of drawing out a printed circuit board to be tested onto the testing X-Y robot, and allows dc operation testing. In a high-speed digital processor, when the printed circuit board is drawn out to a testing support table, testing cannot be carried out in a proper operation state because of the effects of a clock delay or a signal waveform disturbance. In the method disclosed in Patent Document, the signal level at each point on the printed circuit board is only monitored. Therefore, an error detection circuit testing which, in a normal state, has difficulty determining an operation state cannot be carried out.
A method of causing a simulated failure to occur by bringing a predetermined point on a printed circuit board into contact with a probe connected to, for example, 0 volts and forcefully performing a 0 volt clamping is available. However, as shown in FIG. 10, since, in general, in an actual information processor 1000, a plurality of printed circuit boards 1001 are disposed in parallel and mounted, in order to bring the probe into contact with each point of a digital circuit while the printed circuit boards 1001 are mounted, it is necessary to insert the probe 1100 having a long lead wire into a gap between the printed circuit boards 1101, 1102 as shown in FIG. 11. However, with the probe 1100 having a long lead wire, a reliable 0 volt clamping cannot be expected in high-speed operation.